Field programmable logic devices such as PLAs and FPGAs sometimes provide storage devices for receiving and storing logic values generated by logic portions of the device. The simplest storage device is a latch, which in one mode passes input date through to the output and in another modes stores an input value present at the time a clock signal causes the latch to store the value. Two latches in series form a D flip flop which has the advantage of being able to move a data signal from input to output at a selected time. More complex flip flops include the T flip flop which toggles (changes state of) the output at a clock edge if the input is high. A JK flip flop receives two signals J and K and provides four output choices in response to the J and K values. If J and K are both low, the Q output signal does not change from a previous value. If J and K are both high, the Q output is switched from its previous value at a clock edge. If J is high and K is low, the Q output becomes high. If K is high and J is low, the Q output becomes low. These three types of flip flops are commonly used by logic designers, and it is, therefore, desirable to obtain at least these three options in a user programmable storage device. Any of these options can be provided by adding appropriate gates to the logic signals which drive the D input of a D flip flop.
In past logic devices, such as those available from Xilinx, Inc. described in the 1992 "The Programmable Gate Array Data Book" available from Xilinx, Inc. 2100 Logic Drive, San Jose, Calif. 95124, a D flip flop is expressly provided, and logic to form the T or JK options with a D flip flop is generated in a lookup table which provides combinatorial functions of its inputs. However, this lookup table consumes a fair amount of chip area to generate a relatively simple function.
Users also frequently desire to provide parallel inputs to a flip flop, selecting one of two inputs or providing a logic function of two inputs as input to a D flip flop. In addition, users may wish to load a flip flop asynchronously, bypassing the clock control. This loading is typically available on set or reset inputs to a D flip flop. However, the set and reset inputs are typically driven by a global signal and are therefore not accessible individually for changing the values in the flip flop.